library verilog;
use verilog.vl_types.all;
entity Left_Shift1 is
    port(
        Left_Shift1_Left_Input: in     vl_logic_vector(28 downto 1);
        Left_Shift1_Right_Input: in     vl_logic_vector(28 downto 1);
        Left_Shift1_Select: in     vl_logic;
        Left_Shift1_Left_Output: out    vl_logic_vector(28 downto 1);
        Left_Shift1_Right_Output: out    vl_logic_vector(28 downto 1);
        Left_Shift1_Finish_Flag: out    vl_logic;
        clk             : in     vl_logic
    );
end Left_Shift1;
